In recent years, electronic devices using NAND flash memory for main storage have been produced in great number. As such electronic devices become increasingly multifunctional, increased storage capacity of NAND flash memory becomes a problem to be addressed (for example, Jpn. Pat. Appln. KOKAI Publication No. 2009-141222).
In order to achieve an increase in storage capacity, chip layout is very important. For example, although miniaturization of a memory cell markedly progresses, in order to solve problems such as disconnection, short-circuit, and the like of conductive lines to improve reliability, sizes or pitches of the shapes of conductive lines and contact holes need to be determined in consideration of difficulty of photolithography and withstand voltages between the conductive lines.
In particular, even though bit lines are formed with a minimum processing dimension using line-and-space patterns, in order to connect a switch element called a bit-line hookup circuit to a bit line, a layout or the like need to be sufficiently devised such that a conductive line is connected with curvature. For example, an increase of a random pattern to be compensated for needs to be suppressed in terms of photolithography. Furthermore, in terms of miniaturization of interconnection pitch, the withstand voltage of a conductive line needs to be secured.
Therefore, an examination of a layout in a bit-line hookup circuit is necessary for securing a margin of photolithography, assurance of withstand voltage between interconnection layers, reduction of chip size, and increase in storage capacity.
However, when miniaturization progresses, in the configuration of a conventional bit-line hookup circuit, the following problem arises.
For example, in a NAND flash memory, in a data erasing operation, a potential difference between interconnection layers in a bit-line hookup circuit is 20 V or more, and a leakage current is generated between the interconnection layers. For this reason, a withstand voltage of the interconnection layer cannot be assured.
In particular, in interconnection layers in a bit-line hookup circuit, when the interconnection layer approaches a sense circuit, the density of conductive lines on the interconnection layer increases. For this reason, it is difficult to secure a margin while securing a distance which satisfies a specification of a withstand voltage.
As described above, in a conventional semiconductor integrated circuit, when miniaturization progresses, a withstand voltage between interconnection layers in a bit-line hookup circuit cannot be assured, and a margin for photolithography cannot be secured.